RISCBoy: Open-Source RISC-V Games Console Explained
12 Jul 2026
What is RISCBoy?
RISCBoy is an open-source portable games console built entirely from scratch — including a custom RISC-V compatible CPU, a raster graphics pipeline and display controller, chip infrastructure components, and a PCB layout designed in KiCad. The entire design is written in synthesisable Verilog 2005 and is intended to fit onto an iCE40-HX8k FPGA, which has 7,680 logic elements.
The technical core
The processor at the heart of RISCBoy supports the RV32IMC instruction set and has passed both the RISC-V compliance suite for RV32IMC instructions and the riscv-formal verification suite — a signal of rigorous correctness testing for an independently developed CPU core. It also supports M-mode CSRs, exceptions, and a simple compliant extension for vectored external interrupts.
For smaller or lower-cost FPGAs, RISCBoy can be reconfigured to use a smaller RV32I variant of the processor, making it adaptable to boards like the iCE40 UP5k.
Hardware and toolchain
FPGA synthesis for the iCE40 target relies entirely on an open-source toolchain: Yosys, nextpnr, and Project Icestorm. The project's Rev A PCB was designed specifically to be compatible with iTead's 4-layer, 5x5 cm prototyping service, which costs $65 for 10 boards — a notably low barrier to entry for hobbyist or small-scale hardware experimentation.
There is also experimental support for the Lattice ECP5 FPGA family, using board files for the LEF5UM5G-85F-EVN evaluation board. Interestingly, this ECP5 build swaps out the external memory setup — 512 kiB, 16-bit wide SRAM — for internal 256 kiB, 32-bit wide synchronous memory, a design trade-off that reflects the platform's differing memory architecture.
Where the project stands
According to the project timeline, development has progressed through three visible stages: the Rev A PCB was designed for iTead's prototyping service, experimental ECP5 support was subsequently added using internal memory, and a Rev B PCB is now pending as the gateware and bootloader mature further.
This staged approach carries some acknowledged risk. The report flags that ECP5 support remains explicitly experimental, meaning functionality there may be incomplete or unstable. Progress on the Rev B PCB is also dependent on further maturation of the gateware and bootloader, which could introduce delays. Additionally, reliance on open-source FPGA toolchains (Yosys, nextpnr, Icestorm) may offer less mature support than proprietary alternatives — a common trade-off in open hardware projects.
What's not yet known
Several details remain unspecified in available information: there's no confirmed project timeline or start date, no information on team size or number of contributors, no data on production status, availability, or end-user pricing, no performance benchmarks (frame rate, resolution, battery life), and no specific open-source license has been named.
Why founders should care
For founders building hardware or devtools products, RISCBoy is a useful case study rather than a market signal. It's likely (though not confirmed) that the project's open-source, community-style development — moving from a compliance-tested CPU core to iterative PCB revisions — reflects a broader pattern in low-cost hardware prototyping that founders could plausibly apply to their own hardware MVP strategies. The use of fully open-source RISC-V and FPGA toolchains suggests it may be increasingly feasible to prototype custom silicon-adjacent products without proprietary tooling costs, though the experimental status of multi-FPGA support indicates this path still involves real technical risk and is not yet optimized for commercial deployment. Founders evaluating similar approaches should weigh the low prototyping costs (as low as $65 for 10 boards) against the uncertainty inherent in maturing gateware, bootloaders, and cross-platform FPGA support.
The bottom line
RISCBoy demonstrates that a fully custom, open-source console — CPU, graphics pipeline, and PCB included — can be built using accessible, low-cost tools and open FPGA toolchains. Its iterative Rev A-to-Rev B development process and experimental multi-FPGA support offer a template worth studying, even though key details on licensing, performance, and commercial readiness remain unavailable.