RISC-V's Ten-Cent Chip Problem: A Founder's Reality Check

A one-year experiment turns critical

About a year ago, developer Dmitry Grinberg switched his entire hardware stack from STM32/ARM over to RISC-V and documented the move in a video. Now he's published a follow-up essay with a pointed title: "RISC-V: They Should Have Known Better." Despite the critical framing, Grinberg is unambiguous about one thing: he says he's "100% sure that RISC-V will own the cheap-as-dirt single-use microcontroller space eventually."

The report does not detail the specific criticisms behind the essay's title beyond that quote — so the exact friction points that led Grinberg to write a critical piece after a year of RISC-V use remain unclear.

The ten-cent chip at the center of it all

The poster child for RISC-V's cost argument is the CH32V003, a microcontroller that costs just US $0.10 and packs 2KB of SRAM and 16KB of flash. For founders building high-volume, low-margin hardware — think disposable electronics or simple IoT sensors — that price point is hard to ignore.

But cost-per-chip isn't the whole story. Grinberg works out of Trinidad and Tobago, and he reports paying between $60 and $200 to ship chips to the island nation. No explanation is given for why the shipping cost swings so widely, but the range alone is a reminder that landed cost, not sticker price, is what matters for hardware sourcing decisions — especially for founders operating outside major manufacturing hubs.

Not just for cheap microcontrollers anymore

The RISC-V lineup isn't confined to dime-store chips. The CH32H417 — a considerably more capable part — runs a QingKe V5F core at 400 MHz alongside a V3F core at 144 MHz, with 896KB of SRAM and 960KB of flash. It also integrates USB 3.2 Gen1 with a 5 Gbps transceiver and a 500 MB/s high-speed interface. That's a meaningful jump from the ten-cent end of the spectrum, and it suggests RISC-V vendors are pushing the architecture toward more demanding embedded applications, not just single-use throwaway designs.

RISC-V's visibility is also climbing in hobbyist and security circles: the Baochip-1x was used inside the badge for DEFCON 34, though the report doesn't specify exactly when relative to Grinberg's essay. Separately, Grinberg says he's about 80% done with a book on using RISC-V with the CH32V003 — no publication timeline is given.

What's still missing from the picture

The report notes several open questions: there's no direct performance, cost, or ecosystem-maturity comparison between RISC-V and ARM/STM32; no detail on what projects Grinberg has actually shipped since switching; and no clarity on the exact DEFCON 34 timing or book release date. In short, the essay raises flags without fully substantiating them in the material available here.

Why founders should care

Cost math likely won't be as simple as the chip price. A ten-cent BOM component is compelling, but logistics — as the $60–$200 shipping range shows — could meaningfully erode that advantage for founders sourcing internationally or in low-volume runs.
RISC-V's capability range is probably widening. With parts like the CH32H417 offering USB 3.2 and near-1MB memory footprints, RISC-V may increasingly be viable for products beyond simple sensors — worth monitoring if your roadmap includes more demanding embedded features.
Adoption signals are growing but still anecdotal. A DEFCON badge design win and a public one-year migration story suggest rising developer interest, but they don't yet constitute proof of ecosystem maturity comparable to ARM/STM32.
A public advocate turning critical is a signal worth watching. Grinberg's move from an enthusiastic switch to a critically-titled essay — even without full details on the complaints — hints that founders evaluating a RISC-V-based hardware stack should probe for friction points (tooling, documentation, supply chain) before committing, rather than assuming the low chip price tells the whole story.

Sources differ implicitly here: the report includes strong pro-RISC-V sentiment (the "100% sure" quote, the DEFCON badge win) alongside an unresolved critical framing in the essay's title, and it does not reconcile the two beyond the one quoted line.